Role Description: FPGA Engineer responsible for Verilog/System Verilog coding and high-speed PCIe designs and protocols.
Key Requirements: Proficient in Verilog/System Verilog, knowledge of front-end tools, experience with PCIe protocols, and static checkers.
Conditions/Benefits: Location: San Jose CA and Austin TX, Day-1 Onsite, with specific mention of Austin, Texas (UK).
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Job description
Location: San Jose CA and Austin TX (Day-1 Onsite).Proficient in Verilog/System Verilog coding constructs.Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting).Experience with high speed PCIe designs and protocols.Experience with Indu...